Various data processing devices, such as integrated circuits that include instruction based processing devices, access interleaved memory arrays that accommodate access rates that are higher than that available with non-interleaved memories. However, memory arrays organized as interleaved memory are not read-while-write accessible because of the pipelined nature in which they are accessed to increase access speed. To provide read-while-write memory capability additional memory arrays have been provided separate from the interleaved memory that is read-while-write accessible.